module project2_datamemory(iClk, MemWrite, Address, WriteData, ReadData);

input iClk,MemWrite;
input [5:0]Address;
input [7:0] WriteData;
output [7:0] ReadData;

reg [7:0] RAM[63:0];

initial begin
	$readmemh("memfile.dat",RAM);
end

assign ReadData=Ram[Address[5:0]];

always @(posedge iClk) begin
if(MemWrite)
	RAM[Address[5:0]]<=WriteData;
end

endmodule
